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19-3029; Rev 1; 2/04
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
General Description
The MAX1124 is a monolithic 10-bit, 250Msps analogto-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 250Msps while consuming only 477mW. At 250Msps and an input frequency of 100MHz, the MAX1124 achieves a spurious-free dynamic range (SFDR) of 71dBc. Its excellent signal-to-noise ratio (SNR) of 57.1dB at 10MHz remains flat (within 1dB) for input tones up to 500MHz. This makes the MAX1124 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems. The MAX1124 requires a single 1.8V supply. The analog input is designed for either differential or singleended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 500MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible, and the data format can be selected to be either two's complement or offset binary. The MAX1124 is available in a 68-pin QFN with exposed paddle (EP) and is specified over the industrial (-40C to +85C) temperature range. For pin-compatible, lower speed versions of the MAX1124, refer to the MAX1122 (170Msps) and the MAX1123 (210Msps) data sheets. For a pin-compatible 8-bit version of the MAX1124, refer to the MAX1121 data sheet. 250Msps Conversion Rate SNR = 56.8dB/55.5dB at fIN = 100MHz/500MHz SFDR = 71dBc/63.8dBc at fIN = 100MHz/500MHz NPR = 54.8dB at fNOTCH = 28.8MHz Single 1.8V Supply 477mW Power Dissipation at 250Msps On-Chip Track-and-Hold and Internal Reference On-Chip Selectable Divide-by-2 Clock Input LVDS Digital Outputs with Data Clock Output Evaluation Kit Available (Order MAX1124EVKIT)
Features
MAX1124
Ordering Information
PART MAX1124EGK TEMP RANGE -40C to +85C PIN-PACKAGE 68 QFN-EP*
*EP = Exposed paddle.
Pin Configuration
TOP VIEW
OGND AGND AGND AGND AVCC OVCC AVCC AVCC ORN ORP D9N D8N D7N
51 D6P 50 D6N 49 D5P 48 D5N 47 D4P 46 D4N 45 OGND 44 OVCC 43 DCLKP 42 DCLKN 41 OVCC 40 D3P 39 D3N 38 D2P 37 D2N 36 D1P 35 D1N
D9P
D8P N.C.
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52
Applications
Wireless and Wired Broadband Communication Cable-Head End Systems Digital Predistortion Receivers Communications Test Equipment Radar and Satellite Subsystems Antenna Array Processing
AVCC AGND REFIO REFADJ AGND AVCC AGND INP INN
1 2 3 4 5 6 7 8 9
EP
MAX1124
AGND 10 AVCC 11 AVCC 12 AVCC 13 AVCC 14 AGND 15 AGND 16 CLKDIV 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AGND
AVCC
CLKP
CLKN
N.C.
OGND
AGND
AGND
AGND
N.C.
N.C.
D0N
D7P
T/B
OVCC
________________________________________________________________ Maxim Integrated Products
OVCC
AVCC
D0P
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
ABSOLUTE MAXIMUM RATINGS
AVCC to AGND ......................................................-0.3V to +2.1V OVCC to OGND .....................................................-0.3V to +2.1V AVCC to OVCC .......................................................-0.3V to +2.1V AGND to OGND ....................................................-0.3V to +0.3V Analog Inputs to AGND ...........................-0.3V to (AVCC + 0.3V) Digital Inputs to AGND.............................-0.3V to (AVCC + 0.3V) REF, REFADJ to AGND............................-0.3V to (AVCC + 0.3V) Digital Outputs to OGND .........................-0.3V to (OVCC + 0.3V) ESD on All Pins (Human Body Model).............................2000V Continuous Power Dissipation (TA = +70C) 68-Pin QFN (derate 41.7mW/C above +70C) .........3333mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100 1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. 25C guaranteed by production test, <25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Transfer Curve Offset Offset Temperature Drift ANALOG INPUTS (INP, INN) Full-Scale Input Voltage Range Full-Scale Range Temperature Drift Common-Mode Input Range Input Capacitance Differential Input Resistance Full-Power Analog Bandwidth REFERENCE (REFIO, REFADJ) Reference Output Voltage Reference Temperature Drift REFADJ Input High Voltage SAMPLING CHARACTERISTICS Maximum Sampling Rate Minimum Sampling Rate fSAMPLE fSAMPLE 250 20 MHz MHz VREFADJ Used to disable the internal reference AVCC 0.3 VREFIO 1.18 1.24 90 1.30 V ppm/C V VCM CIN RIN FPBW Figure 8 3.00 VFS (Note 1) 1100 1250 130 1.38 0.18 3 4.3 600 6.25 1375 mVP-P ppm/C V pF k MHz INL DNL VOS (Note 1) No missing codes (Note 1) (Note 1) TA +25C (Note 2) 10 -2.4 -1.0 -25 -37 20 0.8 0.5 +2.4 +1.5 +25 +37 Bits LSB LSB LSB V/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100 1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. 25C guaranteed by production test, <25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Clock Duty Cycle Aperture Delay Aperture Jitter CLOCK INPUTS (CLKP, CLKN) Differential Clock Input Amplitude Clock Input Common-Mode Voltage Range Clock Differential Input Resistance Clock Differential Input Capacitance RCLK CCLK (Note 2) 200 500 1.15 0.25 11 25% 5 mVP-P V k pF tAD tAJ SYMBOL CONDITIONS Set by clock management circuit MIN TYP 40 to 60 350 0.2 MAX UNITS % ps psRMS
MAX1124
DYNAMIC CHARACTERISTICS (at -0.5dBFS) fIN = 10MHz, TA +25C Signal-to-Noise Ratio SNR fIN = 100MHz, TA +25C fIN = 180MHz fIN = 500MHz fIN = 10MHz, TA +25C Signal-to-Noise and Distortion SINAD fIN = 100MHz, TA +25C fIN = 180MHz fIN = 500MHz fIN = 10MHz, TA +25C Spurious-Free Dynamic Range SFDR fIN = 100MHz, TA +25C fIN = 180MHz fIN = 500MHz fIN = 10MHz Worst Harmonics (HD2 or HD3) fIN = 100MHz fIN = 180MHz fIN = 500MHz Two-Tone Intermodulation Distortion IMD100 IMD500 fIN1 = 99MHz at -7dBFS, fIN2 = 101MHz at -7dBFS fIN1 = 498.5MHz at -7dBFS, fIN2 = 502.5MHz at -7dBFS 250 62.6 62 54 53.5 54.3 54 57.1 56.8 56.3 55.5 57 56.5 56 55 75 71 68.3 63.8 -75 -71 -68.3 -63.8 -65 dBc -56 dBc dBc dB dB
LVDS DIGITAL OUTPUTS (D0P/N-D9P/N, DCLKP/N) Differential Output Voltage |VOD| 400 mV
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3
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100 1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. 25C guaranteed by production test, <25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Output Offset Voltage SYMBOL OVOS CONDITIONS MIN 1.125 TYP MAX 1.310 0.2 x AVCC 0.8 x AVCC Figure 4 Figure 4 Figure 4 (Note 2) 20% to 80%, CL = 5pF 20% to 80%, CL = 5pF 0.92 1.5 2.85 1.35 460 460 8 1.86 UNITS V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B) Digital Input Voltage Low Digital Input Voltage High TIMING CHARACTERISTICS CLK to Data Propagation Delay CLK to DCLK Propagation Delay Data Valid to DCLK Rising Edge LVDS Output Rise-Time LVDS Output Fall-Time Output Data Pipeline Delay POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range Analog Supply Digital Supply Current Analog Power Dissipation Power-Supply Rejection Ratio (Note 3) AVCC OVCC IAVCC IOVCC PDISS PSRR fIN = 100MHz fIN = 100MHz fIN = 100MHz Offset Gain 1.7 1.7 1.8 1.8 220 45 477 1.6 1.9 1.9 1.9 290 75 657 V V mA mA mW mV/V %FS/V tPDL tCPDL tCPDL tPDL tRISE tFALL tLATENCY ns ns ns ps ps Clock cycles VIL VIH V V
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The fullscale range is defined as 1023 x slope of the line. Note 2: Parameter guaranteed by design and characterization; TA = TMIN to TMAX. Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
Typical Operating Characteristics
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA = +25C.)
FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING)
MAX1124 toc01
FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING)
MAX1124 toc02
FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING)
-10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 HD3 HD2 fSAMPLE = 250.0057MHz fIN = 183.5064MHz AIN = -0.5335dBFS SNR = 56dB SFDR = 68.7dBc HD2 = -78.1dBc HD3 = -68.7dBc
MAX1124 toc03 MAX1124 toc09 MAX1124 toc06
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 100 120 HD2 HD3 fSAMPLE = 250.0057MHz fIN = 11.5054MHz AIN = -0.4795dBFS SNR = 56.5dB SFDR = 73.5dBc HD2 = -82.4dBc HD3 = -73.5dBc
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 HD3 fSAMPLE = 250.0057MHz fIN = 60.0294MHz AIN = -0.4885dBFS SNR = 56.4dB SFDR = 74.6dBc HD2 = -82.1dBc HD3 = -75.6dBc
0
HD2
140
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING)
-10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 100 120 ANALOG INPUT FREQUENCY (MHz) 140 51 50 HD2 HD3 FUNDAMENTAL fSAMPLE = 250.0057MHz fIN = 500.516MHz AIN = -0.5155dBFS SNR = 55.4dB SFDR = 64.8dBc HD2 = -69.9dBc HD3 = -64.8dBc
MAX1124 toc04
SNR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc05
SFDR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
80 75 70 65 SFDR (dBc)
0
58 57 56 55 SNR (dB) 54 53 52
60 55 50 45 40 35 30
0
100
200
300
400
500
0
100
200
300
400
500
fIN (MHz)
fIN (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY (fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc07
SNR vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 250.0057MHz, fIN = 60.0294MHz)
MAX1124 toc08
SFDR vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 250.0057MHz, fIN = 60.0294MHz)
80 75 70 SFDR (dBc) 65 60 55
-50
62 57 52
-60 HD2/HD3 (dBc)
HD3
SNR (dB) HD2
-70
47 42 37
-80
-90 32 -100 0 100 200 300 400 500 fIN (MHz) 27 -28 -24 -20 -16 -12 -8 -4 0 ANALOG INPUT AMPLITUDE (dBFS)
50 45 40 -28 -24 -20 -16 -12 -8 -4 0 ANALOG INPUT AMPLITUDE (dBFS)
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5
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA = +25C.)
HD2/HD3 vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 250.0057MHz, fIN = 60.0294MHz)
MAX1124 toc10
SNR vs. fSAMPLE (fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1124 toc11
SFDR vs. fSAMPLE (fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1124 toc12
-40 -45 -50 HD2/HD3 (dBc) -55 -60 -65 -70 -75 -80 -85 -90 -28 -24 -20 -16 -12 -8 -4 0 ANALOG INPUT AMPLITUDE (dBFS) HD2 HD3
58 57 56
90
80
54 53 52
SFDR (dBc) 10 50 90 130 170 210 250
55 SNR (dB)
70
60
50 51 50 fSAMPLE (MHz) 40 10 50 90 130 170 210 250 fSAMPLE (MHz)
HD2/HD3 vs. fSAMPLE (fIN = 60.03294MHz, AIN = -0.5dBFS)
MAX1124 toc13
TWO-TONE IMD PLOT (8192-POINT DATA RECORD, COHERENT SAMPLING)
-10 -20 -30 AMPLITUDE (dB) fSAMPLE = 250.0057MHz fIN1 = 99.0317MHz fIN2 = 101.0459MHz AIN1 = AIN2 = -7dBFS IMD = -65dBc
MAX1124 toc14
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.8 0.6 0.4
MAX1124 toc15
-60 -65 -70 HD2/HD3 (dBc) -75 -80 -85 -90 -95 -100 10 50 90 130 170 210 HD2 HD3
0
1.0
-50 -60 -70 -80 -90 2fIN1 - fIN2
2fIN2 fIN1
INL (LSB)
-40
fIN1
fIN2
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
250
-100 0 20 40 60 80 100 120 140 ANALOG INPUT FREQUENCY (MHz)
0
128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
fSAMPLE (MHz)
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1124 toc16
GAIN BANDWIDTH PLOT (fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc17
SNR vs. TEMPERATURE (fIN = 65.0344MHz, fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
59 58 57 SNR (dB) 56 55 54 53 52
MAX1124 toc18
0.6 0.4 0.2 DNL (LSB)
2 0 -2 GAIN (dB) -4 -6 -8 -10 -12
60
0 -0.2 -0.4 -0.6 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
51 50 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 -40 -15 10 35 60 85 TEMPERATURE (C)
6
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA = +25C.)
SINAD vs. TEMPERATURE (fIN = 65.0344MHz, fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc19
SFDR vs. TEMPERATURE (fIN = 65.0344MHz, fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124 toc20
59 58 57 SINAD (dB)
75 70 SFDR (dBc) 65 60 55
495 485 PDISS (mW) 475 465 455 445 435
56 55 54 53 52 51 50 -40 -15 10 35 60 85 TEMPERATURE (C)
50 -40 -15 10 35 60 85 TEMPERATURE (C)
425 10 50 90 130 170 210 250 fSAMPLE (MHz)
FS VOLTAGE vs. FS ADJUST RESISTOR
MAX1124 toc22
SNR vs. VOLTAGE SUPPLY (fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1124 toc23
FIGURE 6 1.32 1.30 1.28 VFS (V) 1.26 1.24 1.22 1.20 1.18 1.16 RESISTOR VALUE APPLIED BETWEEN REFADJ AND REFIO RESISTOR VALUE APPLIED BETWEEN REFADJ AND AGND
59 58 57 SNR (dB) 56 55 54 53 52 51 50
AVCC = OVCC
MEASURED AT THE REFIO PIN REFADJ = AVCC = OVCC
1.2340
VREFIO (V)
1.2330
1.2320
1.2310
0 100 200 300 400 500 600 700 800 900 1000 FS ADJUST RESISTOR ()
1.5
1.6
1.7
1.8
1.9
2.0
2.1
1.2300 1.5 1.6 1.7 1.8 1.9 2.0 2.1 SUPPLY VOLTAGE (V)
VOLTAGE SUPPLY (V)
NOISE HISTOGRAM (DC INPUT, 128k-POINT DATA RECORD)
MAX1124 toc25
PROPAGATION DELAY TIMES vs. TEMPERATURE
MAX1124 toc26
8.0E+04 7.0E+04 6.0E+04 CODE COUNTS 5.0E+04 4.0E+04 3.0E+04 2.0E+04 1.0E+04 0.0E+00 295 507
74401
fSAMPLE = 250MHz
6 5 PROPAGATION DELAY (ns) 4 3 2 1
56333
tCPDL
43 508 509 510 511 DIGITAL OUTPUT NOISE
tPDL
0 -40 -15 10 35 60 85 TEMPERATURE (C)
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7
MAX1124 toc24
1.34
INTERNAL REFERENCE vs. SUPPLY VOLTAGE (fSAMPLE = 250.0057MHz)
1.2350
60
MAX1124 toc21
60
80
POWER DISSIPATION vs. fSAMPLE (fIN = 60.0294MHz, AIN = -0.5dBFS)
505
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA = +25C.)
SINAD vs. CLOCK DUTY CYCLE (fIN = 1.8148MHz, fSAMPLE = 249.856MHz, AIN = -0.5dBFS)
MAX1124 toc27
NOISE POWER RATIO PLOT
-40 POWER SPECTRAL DENSITY (dB) -50 -60 -70 -80 -90 -100 fSAMPLE = 250MHz fNOTCH = 28.8MHz NPR = 54.8dB 5 10 15 20 25 30 35
MAX1124 toc28
60 59 58 57 SINAD (dB) 56 55 54 53 52 51 50 30 36 42 48 54 60 66
72
CLOCK DUTY CYCLE (%)
ANALOG INPUT FREQUENCY (MHz)
Pin Description
PIN 1, 6, 11-14, 20, 25, 62, 63, 65 2, 5, 7, 10, 15, 16, 18, 19, 21, 24, 64, 66, 67, EP NAME AVCC FUNCTION Analog Supply Voltage. Bypass each pin with a 0.1F capacitor for best decoupling results.
AGND
Analog Converter Ground. Connect the converter's exposed paddle (EP) to AGND.
3
REFIO
Reference Input/Output. With REFADJ pulled high through a 1k resistor, this I/O port allows an external reference source to be connected to the MAX1124. With REFADJ pulled low through the same 1k resistor, the internal 1.23V bandgap reference is active. Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and REFIO (increases FS range). If REFADJ is connected to AVCC through a 1k resistor, the internal reference can be overdriven with an external source connected to REFIO. If REFADJ is connected to AGND through a 1k resistor, the internal reference is used to determine the full-scale range of the data converter. Positive Analog Input Terminal Negative Analog Input Terminal Clock Divider Input. This LVCMOS-compatible input controls which speed the converter's digital outputs are updated. CLKDIV has an internal pulldown resistor. CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate. CLKDIV = 1: ADC updates digital outputs at the input clock rate. True Clock Input. This input requires an LVDS-compatible input level to maintain the converter's excellent performance. Complementary Clock Input. This input requires an LVDS-compatible input level to maintain the converter's excellent performance.
4
REFADJ
8 9
INP INN
17
CLKDIV
22 23
CLKP CLKN
8
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
Pin Description (continued)
PIN 26, 45, 61 27, 28, 41, 44, 60 29-32 33 34 35 36 37 38 39 40 42 NAME OGND OVCC N.C. D0N D0P D1N D1P D2N D2P D3N D3P DCLKN FUNCTION Digital Converter Ground. Ground connection for digital circuitry and output drivers. Digital Supply Voltage. Bypass with a 0.1F capacitor for best decoupling results. No Connection. Do not connect to these pins. Complementary Output Bit 0 (LSB) True Output Bit 0 (LSB) Complementary Output Bit 1 True Output Bit 1 Complementary Output Bit 2 True Output Bit 2 Complementary Output Bit 3 True Output Bit 3 Complementary Clock Output. This output provides an LVDS-compatible output level and can be used to synchronize external devices to the converter clock. There is a 2.1ns delay between CLKN and DCLKN. True Clock Output. This output provides an LVDS-compatible output level and can be used to synchronize external devices to the converter clock. There is a 2.1ns delay between CLKP and DCLKP. Complementary Output Bit 4 True Output Bit 4 Complementary Output Bit 5 True Output Bit 5 Complementary Output Bit 6 True Output Bit 6 Complementary Output Bit 7 True Output Bit 7 Complementary Output Bit 8 True Output Bit 8 Complementary Output Bit 9 (MSB) True Output Bit 9 (MSB) Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORN flags this condition by transitioning low. True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP flags this condition by transitioning high. Two's Complement or Binary Output Format Selection. This LVCMOS-compatible input controls the digital output format of the MAX1124. T/B has an internal pulldown resistor. T/B = 0: Two's complement output format T/B = 1: Binary output format
MAX1124
43 46 47 48 49 50 51 52 53 54 55 56 57 58 59
DCLKP D4N D4P D5N D5P D6N D6P D7N D7P D8N D8P D9N D9P ORN ORP
68
T/B
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9
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
CLKDIV DCLKP DCLKN
CLKP CLKN
CLOCKDIVIDER CONTROL INPUT BUFFER
CLOCK MANAGEMENT
INP INN 2.2k 2.2k
T/H
10-BIT PIPELINE QUANTIZER CORE
LVDS DATA PORT 10
D0P/N-D9P/N
REFERENCE COMMON-MODE BUFFER REFIO REFADJ
ORP ORN
MAX1124
Figure 1. MAX1124 Block Diagram
AVCC
ADC FULL-SCALE = REFT - REFB REFT
INP 2.2k 2.2k
INN
REFB REFERENCE BUFFER
G
REFERENCE SCALING AMPLIFIER
REFIO 0.1F
1V
TO COMMON-MODE INPUT
TO COMMON-MODE INPUT AGND
CONTROL LINE TO DISABLE REFERENCE BUFFER
REFADJ 1k
Figure 2. Simplified Analog Input Architecture
Detailed Description--Theory of Operation
The MAX1124 uses a fully differential, pipelined architecture that allows for high-speed conversion, optimized accuracy and linearity, while minimizing power consumption and die size. Both positive (INP) and negative/complementary analog input terminals (INN) are centered around a commonmode voltage of 1.4V, and accept a differential analog input voltage swing of 0.3125V each, resulting in a typical differential full-scale signal swing of 1.25VP-P. INP and INN are buffered prior to entering each trackand-hold (T/H) stage and are sampled when the differential sampling clock signal transitions high. A 2-bit ADC following the first T/H stage then digitizes the signal, and controls a 2-bit digital-to-analog converter (DAC).
10
AVCC
AVCC / 2
Figure 3. Simplified Reference Architecture
Digitized and reference signals are then subtracted, resulting in a fractional residue signal that is amplified before it is passed on to the next stage through another T/H amplifier. This process is repeated until the applied input signal has successfully passed through all stages of the 10-bit quantizer. Finally, the digital outputs of all stages are combined and corrected for in the digital correction logic to generate the final output code. The result is a 10-bit parallel digital output word in user-selectable two's complement or binary output formats with LVDScompatible output levels. See Figure 1 for a more detailed view of the MAX1124 architecture.
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT INN
INP tAD CLKN N CLKP tCPDL tLATENCY DCLKP N-8 DCLKN tPDL tCPDL - tPDL N-7 N N+1 N+1 N+8 N+9 tCH tCL
D0P/N-D9P/N ORP/N
N-8
N-7
N-1
N
N+1
tCPDL - tPDL ~ 0.4 x tSAMPLE with tSAMPLE = 1/fSAMPLE NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the MAX1124. Differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced AC performance as the signals are progressing through the analog stages. The MAX1124 analog inputs are selfbiased at a common-mode voltage of 1.4V and allow a differential input voltage swing of 1.25VP-P. Both inputs are self-biased through 2.2k resistors, resulting in a typical differential input resistance of 4.4k. It is recommended to drive the analog inputs of the MAX1124 in AC-coupled configuration to achieve best dynamic performance. See the AC-Coupled Analog Inputs section for a detailed discussion of this configuration.
OVCC
VOP
VON
2.2k
2.2k
On-Chip Reference Circuit
The MAX1124 features an internal 1.23V bandgap reference circuit (Figure 3), which, in combination with an internal reference-scaling amplifier, determines the fullscale range of the MAX1124. Bypass REFIO with a 0.1F capacitor to AGND. To compensate for gain errors or increase the ADC's full-scale range, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100k trim potentiometer) between REFADJ and AGND or REFADJ and REFIO. See the Applications Information section for a detailed description of this process.
OGND
Figure 5. Simplified LVDS Output Architecture
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is recommended to drive the clock inputs of the MAX1124
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
Table 1. MAX1124 Digital Output Coding
INP ANALOG VOLTAGE LEVEL INN ANALOG VOLTAGE LEVEL OUT-OF-RANGE ORP (ORN) BINARY DIGITAL OUTPUT CODE (D9-D0) 11 1111 1111 (exceeds positive full scale, OR set) 11 1111 1111 (represents positive full scale) 10 0000 0000 or 01 1111 1111 (represents midscale) 00 0000 0000 (represents negative full scale) 00 0000 0000 (exceeds negative full scale, OR set) TWO'S COMPLEMENT DIGITAL OUTPUT CODE (D9-D0) 01 1111 1111 (exceeds positive full scale, OR set) 01 1111 1111 (represents positive full scale) 00 0000 0000 or 11 1111 1111 (represents midscale) 10 0000 0000 (represents negative full scale) 10 0000 0000 (exceeds negative full scale, OR set)
> VCM + 0.3125V
< VCM - 0.3125V
1 (0)
VCM + 0.3125V
VCM - 0.3125V
0 (1)
VCM
VCM
0 (1)
VCM - 0.3125V
VCM + 0.3125V
0 (1)
< VCM - 0.3125V
> VCM + 0.3125V
1 (0)
with an LVDS-compatible clock to achieve the best dynamic performance. The clock signal source must be a high-quality, low phase noise to avoid any degradation in the noise performance of the ADC. The clock inputs (CLKP, CLKN) are internally biased to 1.2V, accept a differential signal swing of 0.2VP-P to 1.0VP-P and are usually driven in AC-coupled configuration. See the Differential, AC-Coupled Clock Input in the Applications Information section for more circuit details on how to drive CLKP and CLKN appropriately. Although not recommended, the clock inputs also accept a single-ended input signal. The MAX1124 also features an internal clock management circuit (duty-cycle equalizer) that ensures that the clock signal applied to inputs CLKP and CLKN is processed to provide a 50% duty cycle clock signal, which desensitizes the performance of the converter to variations in the duty cycle of the input clock source. Note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum clock frequency of >20MHz to work appropriately and according to data sheet specifications.
can be used to synchronize external devices (e.g., FPGAs) to the ADC. DCLKP and DCLKN are differential outputs with LVDS-compatible voltage levels. There is a 2.1ns delay time between the rising (falling) edge of CLKP (CLKN) and the rising edge of DCLKP (DCLKN). See Figure 4 for timing details.
Divide-by-2 Clock Control (CLKDIV)
The MAX1124 offers a clock control line (CLKDIV), which supports the reduction of clock jitter in a system. Connect CLKDIV to OGND to enable the ADC's internal divide-by-2 clock divider. Data is now updated at onehalf the ADC's input clock rate. CLKDIV has an internal pulldown resistor and can be left open for applications that only operate with update rates one-half of the converter's sampling rate. Connecting CLKDIV to OVCC allows data to be updated at the speed of the ADC input clock.
System Timing Requirements
Figure 4 depicts the relationship between the clock input and output, analog input, sampling event, and data output. The MAX1124 samples on the rising (falling) edge of CLKP (CLKN). Output data is valid on the next rising (falling) edge of the DCLKP (DCLKN) clock, but has an internal latency of nine clock cycles.
Clock Outputs (DCLKP, DCLKN)
The MAX1124 features a differential clock output, which can be used to latch the digital output data with an external latch or receiver. Additionally, the clock output
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
Digital Outputs (D0P/N-D9P/N, DCLKP/N, ORP/N) and Control Input T/B
The digital outputs D0P/N-D9P/N, DCLKP/N, and ORP/N are LVDS compatible, and data on D0P/N-D9P/N is presented in either binary or two's complement format (Table 1). The T/B control line is an LVCMOS-compatible input, which allows the user to select the desired output format. Pulling T/B low outputs data in two's complement and pulling it high presents data in offset binary format on the 10-bit parallel bus. T/B has an internal pulldown resistor and may be left unconnected in applications using only two's complement output format. All LVDS outputs provide a typical voltage swing of 0.4V around a common-mode voltage of approximately 1.2V, and must be terminated at the far end of each transmission line pair (true and complementary) with 100. The LVDS outputs are powered from a separate power supply, which can be operated between 1.7V and 1.9V. The MAX1124 offers an additional differential output pair (ORP, ORN) to flag out-of-range conditions, where out of range is above positive or below negative full scale. An out-of-range condition is identified with ORP (ORN) transitioning high (low). Note: Although differential LVDS reduces single-ended transients to the supply and ground planes, capacitive loading on the digital outputs should still be kept as low as possible. Using LVDS buffers on the digital outputs of the ADC when driving off-board may improve overall performance and reduce system timing constraints.
MAX1124
ADC FULL-SCALE = REFT - REFB REFT REFB REFERENCE BUFFER G
REFERENCESCALING AMPLIFIER
REFIO 0.1F 1V REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER 13k TO 1M
13k TO 1M
AVCC
AVCC / 2
Figure 6. Circuit Suggestions to Adjust the ADC's Full-Scale Range
Applications Information
Full-Scale Range Adjustments Using the Internal Bandgap Reference
The MAX1124 supports a full-scale adjustment range of 10% (5%). To decrease the full-scale range, an external resistor value ranging from 13k to 1M may be added between REFADJ and AGND. A similar approach can be taken to increase the ADCs full-scale range. Adding a variable resistor, potentiometer, or
VCLK 0.1F
8 SINGLE-ENDED INPUT TERMINAL 0.1F 0.1F 7 2 MC100LVEL16 50 3 6 CLKN CLKP D0P/N-D9P/N 150 0.1F AVCC OVCC
510
510 4 0.01F 5
150
INP
MAX1124
INN 10
VGND AGND OGND
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration ______________________________________________________________________________________ 13
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
AVCC SINGLE-ENDED INPUT TERMINAL 0.1F OVCC
ADT1-1WT 25
15
INP
D0P/N-D9P/N
25
15
MAX1124
INN 10
0.1F AGND OGND
Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination
predetermined resistor value between REFADJ and REFIO increases the full-scale range of the data converter. Figure 6 shows the two possible configurations and their impact on the overall full-scale range adjustment of the MAX1124. Do not use resistor values of less than 13k to avoid instability of the internal gain regulation loop for the bandgap reference.
AVCC SINGLE-ENDED INPUT TERMINAL
OVCC
0.1F INP D0P/N-D9P/N 50 0.1F INN 25 AGND OGND
MAX1124
10
Differential, AC-Coupled, PECL-Compatible Clock Input
The preferred method of clocking the MAX1124 is differentially with LVDS- or PECL-compatible input levels. To accomplish this, a 50 reverse-terminated clock signal source with low phase noise is AC-coupled into a fast differential receiver such as the MC100LVEL16 (Figure 7). The receiver produces the necessary PECL output levels to drive the clock inputs of the data converter.
Figure 9. Single-Ended AC-Coupled Analog Input Configuration
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX1124 can be used in single-ended mode (Figure 9). Analog signals can be AC-coupled to the positive input INP through a 0.1F capacitor and terminated with a 50 resistor to AGND. The negative input should be 25 reverse-terminated and AC grounded with a 0.1F capacitor.
Differential, AC-Coupled Analog Input
An RF transformer provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1124 for optimum dynamic performance. In general, the MAX1124 provides the best SFDR and THD with fully differential input signals and it is not recommended to drive the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics are usually lower since INP and INN are balanced, and each of the ADC inputs only requires half the signal swing compared to a single-ended configuration. Figure 8 depicts a secondary-side termination of the 1:1 transformer into two separate 25 loads. Terminating the transformer in this fashion reduces the potential effects of transformer parasitics. The source impedance combined with the shunt capacitance provided by a PC board and the ADC's parasitic capacitance reduce the combined bandwidth to approximately 550MHz.
14
Grounding, Bypassing, and Board Layout Considerations
The MAX1124 requires board layout design techniques suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The analog and digital supply voltage pins accept input voltage ranges of 1.7V to 1.9V. Although both supply types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by digital switching currents, which can couple into the analog supply network. Isolate analog and digital supplies (AVCC and OVCC) where they enter the PC board with separate
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
BYPASSING--ADC LEVEL AVCC OVCC BYPASSING--BOARD LEVEL AVCC
0.1F
0.1F
1F
10F
47F
ANALOG POWERSUPPLY SOURCE
AGND
OGND D0P/N-D9P/N OVCC
MAX1124
10 1F AGND OGND 10F 47F DIGITAL/OUTPUTDRIVER POWERSUPPLY SOURCE
NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL) SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1F CAPACITOR CLOSE TO THE ADC.
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1124
networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND). To achieve optimum performance, provide each supply with a separate network of a 47F tantalum capacitor in parallel with 10F and 1F ceramic capacitors. Additionally, the ADC requires each supply pin to be bypassed with separate 0.1F ceramic capacitors (Figure 10). Locate these capacitors directly at the ADC supply pins or as close as possible to the MAX1124. Choose surface-mount capacitors, which are preferably located on the same side as the converter, to save space and minimize the inductance. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the ADC's package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. A major concern with this approach are the dynamic currents that may need to travel long distances before they are recombined at a common source ground, resulting in large and undesirable ground loops. Ground loops can add to digital noise by coupling back to the analog front end of the converter, resulting in increased spur activity and a decreased noise performance. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sections of the ADC. This does not require additional ground splitting, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. The MAX1124 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater design flexibility, increased thermal efficiency, and optimized AC performance of the ADC. The EP must be soldered down to AGND. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR) flow soldering techniques. Note that thermal efficiency is not the key factor, since the MAX1124 features low-power operation. The exposed pad is the key element to ensure a solid ground connection between the DAC and the PC board's analog ground layer. Considerable care must be taken, when routing the digital output traces for a high-speed, high-resolution data converter. It is essential to keep trace lengths at a minimum and place minimal capacitive loading--less than 5pF--on any digital trace to prevent coupling to sensitive analog sections of the ADC. It is recommended to run the LVDS output traces as differential lines
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1124
with 100 characteristic impedance from the ADC to the LVDS load device.
CLKP CLKN
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. However, the static linearity parameters for the MAX1124 are measured using the histogram method with an input frequency of 10MHz.
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
Differential Nonlinearly (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. The MAX1124's DNL specification is measured with the histogram method based on a 10MHz input tone.
T/H
TRACK
HOLD
TRACK
Figure 11. Aperture Jitter/Delay Specifications
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the ADC's full-scale range.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 11).
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the SNR calculation and should be considered when determining the SNR in ADC.
Pin-Compatible Higher Speed/ Lower Resolution Versions
PART MAX1122 MAX1123 MAX1121 RESOLUTION (Bits) 10 10 8 SPEED GRADE (Msps) 170 210 250
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In case of the MAX1124, SINAD is computed from a curve fit.
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1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
68L QFN.EPS
MAX1124
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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